This invention relates to a data processing system.
In the manner which will later be described, the data processing system comprises a main memory comprising a program area and a data area. The program area is for memorizing a channel program including bits representative of a channel command and of a logical data address. The data processing system is for use in combination with at least one peripheral device, which may be a disk memory, a magnetic tape memory, or a display device.
In a conventional data processing system, an input-output processor responds to the bits representative of the channel command received from the program area. In this event, the input-output processor requests data transfer between the data area of the main memory and a peripheral controller coupled to the input-output processor and to the peripheral device when the data transfer is indicated by the channel command represented by the bits received from the program area. For this purpose, the input-output processor produces a translation request signal in response to the channel command which indicates the data transfer. Responsive to the translation request signal, a central processor translates into a physical data address the logical data address which accompanies the channel command and is represented by the bits received from the program area. On transferring data from the data area of the main memory to the peripheral device through the input-output processor and the peripheral controller, the input-output processor produces a read command signal in response to the physical data address which is represented by a signal received from the central processor. In a similar manner, the input-output processor produces a write command signal for use in transferring data from the peripheral device to the data area.
Inasmuch as the input-output processor requests the data transfer, the input-output processor must administrate the logical data address and also the physical data address into which the logical data address is translated. When the number of the peripheral controllers is increased in order to deal with a large number of peripheral devices, the input-output processor is subjected to overhead. Thus, the data processing system is incapable of efficiently controlling a large number of peripheral devices.
Such a conventional data processing system is disclosed, for example, in U.S. Pat. No. 4,224,667 issued to David O. Lewis et al and assigned to International Business Machines Corporation in Armonk, N.Y.. In the Lewis et al U.S. patent, the peripheral controller, the peripheral device, and the central processor are called an I/O adapter, an I/O device, and a central processing unit (CPU), respectively. The input-output processor may correspond to a combination of an I/O channel and a virtual address translator (VAT). Although an input-output (I/O) command including device address data and command data is transferred from a main storage or memory to the I/O adapter, the I/O adapter does not receive the above-mentioned channel command which indicates the data transfer and is accompanied by the logical data address.